| 8:30-9:30 |
Breakfast and Registration |
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|
| 9:30-10:15 |
Welcome and Project Overview |
Philip Levis |
DAM Director |
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Session: Devices and Memory
|
| 10:15-10:45 |
Memory Scaling |
Mark Horowitz |
Faculty |
| 10:45-11:15 |
Harnessing data transience for next-generation AI efficiency |
Thierry Tambe |
Faculty |
| 11:15-11:30 |
Break |
|
|
| 11:30-12:00 |
Gain Cell Memory: Technology Integration and Memory Access |
H.-S. Philip Wong |
Faculty |
|
Lunch, 12-1, Allen Patio
|
|
Session: Architecture
|
| 1:00-1:30 |
Computation Immersed in Memory Architectures |
Subhasish Mitra |
Faculty |
| 1:30-2:00 |
Orchestrating Coherence and Consistency in Heterogeneous Shared Memory Systems |
Caroline Trippel |
Faculty |
| 2:00-2:15 |
Coffee break |
|
|
|
Session: Operating Systems and Applications
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| 2:15-2:45 |
Operating System Management of Heterogeneous Memory |
Philip Levis |
Faculty |
| 2:45-3:15 |
Fine-grained dataflow visibility and I/O-compute separation |
Keith Winstein |
Faculty |
| 3:15-3:45 |
Tour of Stanford Nano-Fabrication Facilities |
H.-S. Philip Wong |
|
Poster Session, 3:45-4:45
- Cornflakes: Zero-Copy Serialization for Microsecond-Scale Networking, Gina Yuan
- MemGlue: An Update-Based Cache Coherence Protocol for Heterogeneous Hardware, Rachel Cleaveland
- Fixpoint: Pack More Serverless Functions in Limited Memroy Resource, Yuhan Deng
- First Experimental Demonstration of Hybrid Gain Cell Memory with Si PMOS and ITO FET for High-speed On-chip Memory, Shuhan Liu
- NIC Priority Queue Integration: Challenges and Opportunities, Colin Drewes
- Bitwise adaptive early termination of hyperdimensional computing, Harry Chen
- New Foundry Monolithic 3D Transistor+Memory Unlocks Large Energy and Delay Benefits vs. Conventional Silicon Transistor+Memory, Robert Radway
- MINOTAUR Illusion: Edge Inference & Training that Scale Across Single- and Multi-Chip System, Robert Radway
|
| 4:45-5:00 |
Closing |
Philip Levis |
|
